Hi Ruud :) a few years ago I bought a w65c816sxb board from wdc removed the wdc monitor and started to develop my own monitor (I removed it simply because the development system from wdc was awful and not documented) I discovered a bug, initially I thought it was in my code, I spent day trying to understand what I did wrong.... then I ported my code to a Vince Briel Replica 1 and it worked perfectly... if you try the following sequence on a 6502 LDA #$FF STA $40 STA $41 LDY #$02 LDA ($40), Y on a 6502 it works, it wrap and return a byte from page 0 in emulation mode on a 65c816 it does not wrap and try to access the same byte but not in bank 00 but in bank 01 if you have memory at that place it return the wrong byte if you don't have memory you get an error I also developed my 65c816 board to investigate this case if you check the schematics of the w65c816sxb you can see that the bank latch is loaded when phi2 goes low I think that by modifying this mechanism we can fix this bug it E = 0 we load the latch when phi2 goes low if E = 1 we reset the latch so it contains 0 (in that case it would access the right byte in page 0 bank 0) my board has: - a 65c6816 - 512k ram - 8 .. 32k eeprom - 65c51 - glue logic in an EPM7128S [this way I can try several scenario to try to fix the bug by taking care of the E flag while loading] in my I'm trying the following rule to load the bank register: bank <= d when e = '0' and phi2 = '0' else x"00"; I discovered another problem, I planned to use a w65c51 on my board but this chip is bugged and unusable.... I"ll replace it by another one from Rockwell but I won't be able to push the speed over 2Mhz I have no idea if my attempt to solve this problem has side effects... frankly for me it is clear that I'll never use other wdc products for me adding a delay after a transmit is not acceptable I was planning to start at 1Mhz then push the speed to it's limits... my final goal was to make an accelerator board for the cbm 8000 with a 65c816 + 128k implementing the base memory + 64k ext plus a possibility to load the rom in memory and use it write protected this is the answer to my question about this problem to WDC (answer from David Gray) > Here is the code snippet that we use in our monitor. We use a 8MHz clock so we calculated the number of cylces needed. > The theory behind it is you write the data register, then you go in a loop long enough to let the data go out the TX line before sending another byte. Here we use the X reg as the count > > > register and decrement and loop. > > ACIA_Write_Byte: > sta ACIA_DR ;65c51 Data TX Port > > phx > > ldx #180 >?L1 dex > bne ?L1 > > plx > On 18/10/2023 21:20, ruud_at_baltissen.org wrote: > Hallo Didier, > > >> after the other infamous bug I found in the 65c816 in emulation mode... > > Please, refresh my mind because it doesn't ring a bell. > >Received on 2023-10-19 12:00:03
Archive generated by hypermail 2.3.0.