On Fri, Jun 15, 2018 at 3:45 PM, Marko Mäkelä <marko.makela@iki.fi> wrote: > Hi, > > On Thu, Jun 14, 2018 at 03:22:56PM +0200, Michał Pleban wrote: >> >> Hello! >> >> Francesco Messineo wrote: >> >>> yes I know how to count macrocells, I just didn't check how many would >>> be needed for a 6526. >>> 128 is quite a lot I would think. >> >> >> A very crude calculation: >> >> * Two 8-bit ports with direction pins: 2x2x8 = 32 that would be actually only 16 macrocells. One of the examples on WinCupl makes 3 x 8 bit ports with DDR on a 32 macrocells CPLD, so the same macrocell it's been used for the port bit and its DD bit (probably different functions of the same FF). The result doesn't change much I think. >> * One 8-bit serial port = 8 + some unknown overhead >> * Two 16-bit counters with preset = 2x2x16 = 64 >> * TOD clock with alarm: 2x28 = 56 >> * Interrupt logic = unknown, but I would assume at least 8-16 >> >> That is already way over 128. > > > These functions are fairly independent of each other. Would it be feasible > to implement the CIA in two CPLDs that would share the address and data bus > interface? yes, that was one of the options I've thought of too. The result should anyway be cheaper than a 6526 and it should more or less fit in its footprint. On the breadbin C64, the spaces where the CIAs live are quite small. By the way, also a possible 7501 replacement should be quite a tight fit on the original footprint. Spaces on C16, C116, Plus4 are different and almost never on the same side of the chip :/ The 6502 to 7501 adapter would fit in a 32 macrocell design, but the ATF1502 lacks enough I/O pins (16 + 16 addresses, they must be tristated on the 7501 side, and 8 + 8 data and we already used all the available ones). By the way, does a 6502 really need a transceiver on the data bus? Does it still drive the data bus during the low clock phase? FReceived on 2018-06-15 17:01:04
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