> On 2018-03-15, at 12:04, smf <smf@null.net> wrote: > > > On 15/03/2018 00:33, silverdr@wfmh.org.pl wrote: >> >> The reason I worry is because I don't fully understand how a chip with no PHI2 input doesn't "get confused" whether _CS going low means a read or write cycle. What happens when _CS goes low with R_W remaining high and THEN going low, as it seems to be the case with SRAM, when _CS comes first and then comes R_W due to external combination waiting for PHI2? Isn't this what Mia called "spurious short reads"? > > It depends on the sram, this one http://www.cnic.ro/ed/ic/CY6264.pdf > > Has two CE1/CE2/OE/WR that are used in different combinations and timing based on whether you are reading or writing. 6264 is the one I use most of the time. Having a choice of active low and active high select lines makes it more flexible when interfacing and employing in various circuits but my typical way (not that I invented it or something) is to use one (/CS) line along with /OE and pull the other (CS) statically up. I never had the need to verify the exact timing because the above always worked. It is now that I feel the need to understand it better, and am still unconvinced if this approach of waiting for PHI2 before allowing R/W to flag write cycle - while required - doesn't cause the "spurious short reads" or bush clashes, etc. Shall probably have to measure this thoroughly once I have a chance to. > This one https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8016.pdf > > Just has CE/OE/WR > > When reading you set the address, enable the chip and finally signal on OE > > When writing you set the address and data, enable the chip and finally signal on WR I have no sequence logic to drive /OE separately. Having one and allowing only either /OE or /WE (WR) to become active would solve the problem. But it would also have to be timed properly, which turns back to PHI2.. oh, boy.. -- SD! - http://e4aws.silverdr.com/Received on 2018-03-15 23:01:09
Archive generated by hypermail 2.2.0.