On 29/06/2016 23:28, Segher Boessenkool wrote: > 4/5/6 does make sense with the cycle descriptions though; or, if it is > constant time (which I seriously doubt), 4 always. And the 65ce02 with the new architecture where all instructions take a constant time. http://archive.6502.org/datasheets/mos_65ce02_mpu.pdf My guess is that bbr/bbs on the 65c02 were constant time, but the adder was still only able to work on 8 bits at a time so it needs an additional cycle. There is circumstantial evidence that bbr & bbs were developed by rockwell and then WDC adopted them later for the 65C02S. They aren't in the 65816, or any of the 65C02 from anyone else. So don't expect them to fit in with the rest of the design. On 29/06/2016 23:28, Segher Boessenkool wrote: > 4510... Not so certain that is the same as 65CE02. Google is pretty convinced that it is. I don't know the provenance of http://www.zimmers.net/cbmpics/cbm/c65/c65manual.txt, but it is the closest thing we have to a manual for the commodore 65 and that says it is. Victor F Andrade on his linked in page says he "Re-designed the 6502 8-bit processor from depletion NMOS to CMOS" at CSG. Although he doesn't say it was the 65CE02, the 65CE02 was done in 1988 and I can't see that CSG would redesign it twice (CSG were only second source for the 65C02). Message was sent through the cbm-hackers mailing listReceived on 2016-06-30 05:00:02
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